Image sensor circuits are used in a variety of different types of digital image capture systems, including products such as scanners, copiers, and digital cameras. The image sensor is typically composed of an array of light-sensitive pixels that are electrically responsive to incident light reflected from an object or scene whose image is to be captured.
The performance of an image capture system depends in large part on the sensitivity of each individual pixel in the sensor array and its immunity from noise. Pixel sensitivity is defined here as being related to the ratio of a change in the pixel output voltage to the photogenerated charge in the pixel. Noise here is defined as small fluctuations in a signal that can be caused by a variety of known sources. An image sensor with increased noise immunity yields sharper, more accurate images in the presence of environmental and other noise.
Improving the sensitivity of each pixel permits a reduction in exposure time which in turn allows the capture of images at a greater rate. This allows the image capture system to capture motion in the scene. In addition to allowing greater frame rate, higher pixel sensitivity also helps detect weaker incident light to capture acceptable quality images under low light conditions.
One way to increase pixel sensitivity is to increase the efficiency of the photodiode by changing the photodiode's responsiveness characteristics. Doing so, however, particularly for a CMOS imager pixel, can require deviating from a standard MOS integrated circuit fabrication process, thereby further increasing the cost of manufacturing the image sensor circuit.
With reference to FIG. 1, which depicts a schematic diagram of a portion of a conventional pixel sensor array 120, a photo-sensitive diode 106 within a pixel 100 is first reset by asserting the RST signal which activates reset transistor 104. Activating reset transistor 104 places a reset voltage (e.g., Vdd) across the photodiode. Then, the photodiode 106 is exposed to incident light which causes the charge stored on the photodiode 106 to dissipate the reset voltage initially across the photodiode 106 in proportion to the intensity of the incident light. After a predetermined time period during which the photodiode 106 is exposed to the incident light and the reset voltage is allowed to dissipate from the photodiode 106 (i.e., the “integration” time), the amount of charge stored on the photodiode 106 is transferred to a sample and hold circuit, via source-follower transistor 108 by asserting the SEL signal at the gate of select transistor 110. The sample and hold circuit is conventionally located at one end of the column line 102 and successively reads out image signal values from each pixel coupled to the column line 102.
After the charge on the photodiode 106 has been read-out, the photodiode 106 is reset by asserting the RST signal at the gate of the reset transistor 104 and the reset potential (e.g., Vdd) which is distributed across the photodiode 106 is read-out onto the column line 102 where it too is sampled by the sample and hold circuit. The amount of incident fight which is detected by the photodiode 106 is computed by subtracting the pixel image signal voltage from the reset voltage.
FIG. 2 depicts a schematic diagram of a conventional row driver circuit 200. The row driver circuit 200 generates the RST signal applied to the gate of reset transistor 104 (of FIG. 1). Transistors 202 and 204 are configured as an inverter with reset bar as the input and the RST signal as the output. As depicted, the RST signal is set at either Vdd or ground, depending upon the logic state of the reset signal. For example, if the reset signal is logic HIGH (e.g., “1”), then reset bar is logic LOW (e.g., “0”). As a result, transistor 202 is active and transistor 204 is inactive and the RST signal is at Vdd. It follows that when the reset signal is logic LOW, transistor 202 is inactive and transistor 204 is active with the RST signal set at ground.
Turning to FIG. 3, a schematic diagram of an alternate conventional row driver circuit 300 for generating the RST signal is depicted. Row driver circuit 300 is used to generate a pumped RST signal to the gate of the reset transistor 104. That is, row driver circuit produces a RST signal at a voltage level higher than Vdd, namely, Vrst_high. For example, when the reset signal is logic HIGH, the RST signal is set at Vrst_high, and when the reset signal is logic LOW, the RST signal is set to ground. Row driver circuit 300 is made up of cross-coupled transistors 302, 304, 306 and 308. The RST signal is generated on signal path 310.
One problem commonly encountered with the pixel reset process is that of leakage current flowing from the reset voltage source (e.g., Vdd of FIG. 1) through the reset transistor 104 and to the photodiode 106 when the reset transistor 104 is not activated (e.g., the RST signal is set to ground). Such leakage current may flow into the photodiode 106 during the integration period and alter the pixel image signal. The introduction of such leakage current, known as gate induced drain leakage (GIDL), and which is a prominent component of pixel noise known as “dark current,” inherently and negatively effects the imaging process. As mentioned above, it is generally desirable to minimize pixel noise, and thus, it is desirable to develop a pixel configuration with reduced GIDL.